Exploiting Speculative Thread-Level Parallelism on a SMT Processor

In this paper we present a run-time mechanism to simultaneously execute multiple threads from a sequential program on a simultaneous multithreaded (SMT) processor. The threads are speculative in the sense that they are created by predicting the future control flow of the program. Moreover, threads are not necessarily independent. Data dependences among simultaneously executed threads may exist. To avoid the serialization that such dependences may cause, inter-thread dependences as well as the values that flow through them are predicted. Speculative threads correspond to different iterations of the same loop, which may significantly reduce the fetch bandwidth requirements since many instructions are shared by several threads. The performance evaluation results show a significant performance improvement when compared with a single-threaded execution, which demonstrates the potential of the mechanism to exploit unused hardware contexts. Moreover, the new processor architecture can achieve an IPC (instructions per cycle) even higher than the peak fetch bandwidth for some programs.